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For simple digital design, verification of the logic in ALTERA DE0 is done.
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What is done? Simulation, synthesis or both?
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I've written VHDL code for square wave generation using DAC(Digital to Analog Converter). What all the components and files required to check the output on Cathode Required Oscilloscope.
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You can program the FPGA and look at the signal with an oscilloscope. If you have a sampling oscilloscope with more bits and wider bandwidth than your DAC, then you can capture a block of samples, and analyze it to see if your DAC meets specifications.
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How about generation of User constrained file in ALTERA.
Please let me know the implementation part in ALTERA DE0 kit.
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You would need to constrain the clock(s) and clock-to-output delays to the DAC. The timing requirements that the FPGA must meet are defined in the DAC datasheet. However, if you are using a DAC on the DE0, then Terasic should have an example constraints file.
Cheers,
Dave
Honored Contributor
