Altera_Forum
Honored Contributor
8 years agoGenerate a bianry code from an integer array?
Hello!
I am trying to work for first time with integer arrays. I am not so used to work with them, and I am not able to compile my code. At first, I have created a package, for the arrays of integers: --- Quote Start --- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; PACKAGE inputnumberrs IS constant longitude : integer := 4; type num is array (longitude-1 to 0) of integer; END; --- Quote End --- BTW, I suppose that I will be able to modify this "longitude" constant for another number in ModelSim, right? Forcing the signal or something i suppose. Then, I have created the entity of another project: --- Quote Start --- entity generator is generic (longitude : integer := 4); port (X, Y : in num; clk : in std_logic); end generator; --- Quote End --- And what I want to do is, for example, itroducing 2314 to X and to generate "0010 0011 0001 0100", so I have tryied this: --- Quote Start --- architecture Behavioral of generator is signal t, u : integer := 0; signal a,b : std_logic_vector (longitude*longitude downto 0); begin process begin wait until CLK'EVENT and CLK = '1'; for i in 0 to (longitud*longitud) loop a(u)<= std_logic_vector(to_unsigned(x,4)); t<= t+1; u <= u + 4 ; end loop; wait; end process; end behavioral; --- Quote End --- The compilation error I get is : Error (10409): VHDL Type Conversion error at generar_numeros.vhd(40): converted type of object near text or symbol "std_logic_vector" must match std_ulogic type of target object and i do not have any idea why it is not compiling. If I write a <= std_logic_vector(to_unsigned(x,4)); , withouth the (U), it compiles but does not work :( Any suggestions?