Forum Discussion
Altera_Forum
Honored Contributor
8 years agoSeveral issues in the code:
1. Your Num type is a null array (ie, it has 0 length) type num is array (longitude-1 to 0) of integer; This is a null array, so has length 0. with an ascending array (using to), the larger number must be on the right. So you need to use: type num is array (0 to longitude-1) of integer; A a descending array (using downto) is the opposite. 2. You have a longitude generic, but the length of the num type is set in the package. So having longitude generic set to anything other than 4 will not work. PS. having a generic called longitude means you've hidden the longitude constant in the inputnumberrs package 3. Your a and b slvs are (16 downto 0) ie. 17 bits long. Did you forget the -1? 4. a(u) is a single bit, the 0th element of the a slv. Also, x is an array of integers. to_unsigned only convers a single integer. You also are using the literal 4, when you should probably be using the generic or constant (see issues above) 5. why have you got a for loop, when you dont use the loop variable, i? 6. I assume this is test code, as this will not synthesis as you have a wait statement at the end of the process. So on the first clock, you set a value of A, and then thats it? 7. t is unused. a <= std_logic_vector(to_unsigned(x,4)) cannot be working with the code you posted, as X is an array of 4 integers, and no to_unsigned function exists to convert multiple integers, unless you have defined it yourself. So, is this just test code? it cannot work on an FPGA.