Forum Discussion
Altera_Forum
Honored Contributor
8 years agoYou are assigning a bit vector to a single bit which isn't possible, a simple issue of VHDL syntax.
You want to write something likea(u+3 downto u)<= std_logic_vector(to_unsigned(x,4)); --- Quote Start --- And what I want to do is, for example, introducing 2314 to X and to generate "0010 0011 0001 0100", so I have tryied this: --- Quote End --- 2314 isn't an array of integer literal, it's either a decimal value or a string respectively character array.