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Alexander_Kobler
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4 years ago
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Gated clock conversion fails due to memory

Hello Intel community,

We use "set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON" for our prototyping system, which contains several memories (RAM, ROM). Up to now, this worked as expected.

With a new component, which requires an additional RAM block, clock gate conversion fails, reason is "memory in the gated clock tree". The newly introduced memory is also listed in the mapper reports, section "Registers Packed Into Inferred Megafunctions", while all other memories are not listed here!?

Does anybody has a suggestion, how to fix this problem?

Thanks & best regards,

Alex

  • Alexander_Kobler's avatar
    Alexander_Kobler
    4 years ago

    Hi,

    Thanks for pointing out these attributes, but unfortunately they do not seem to have an impact on clock gate conversion (CGC)

    But I've found a solution: instead of using a single write enable (WE) for a 13 bit data word, I've used a WE for each 8 bit data slice. This seems to help the compiler to find a RAM block which is suitable for CGC

    Instead of:

      wire s_wen;
  assign s_wen = (~CEN) ? WEN : 1'b1;

    Changed to:

    wire [1:0] s_wen;
assign s_wen = {2 {(~CEN) ? WEN : 1'b1}};

    See also attached files.

    Regards

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