Forum Discussion
New ContributorGated clock conversion fails due to memory
Hi,
Thanks for pointing out these attributes, but unfortunately they do not seem to have an impact on clock gate conversion (CGC)
But I've found a solution: instead of using a single write enable (WE) for a 13 bit data word, I've used a WE for each 8 bit data slice. This seems to help the compiler to find a RAM block which is suitable for CGC
Instead of:
wire s_wen; assign s_wen = (~CEN) ? WEN : 1'b1;Changed to:
wire [1:0] s_wen; assign s_wen = {2 {(~CEN) ? WEN : 1'b1}};See also attached files.
Regards
Regular ContributorHi,
You may use below two settings in the QSF file.
RAMSTYLE_ATTRIBUTE: https://www.intel.com/content/www/us/en/programmable/documentation/eca1490998903550.html#analysissynthesisassignmentsramstyleattribute
BLOCK_RAM_TO_MLAB_CELL_CONVERSION: https://www.intel.com/content/www/us/en/programmable/documentation/eca1490998903550.html#fitterassignmentsblockramtomlabcellconversion
Regards
New ContributorHi,
Thanks for pointing out these attributes, but unfortunately they do not seem to have an impact on clock gate conversion (CGC)
But I've found a solution: instead of using a single write enable (WE) for a 13 bit data word, I've used a WE for each 8 bit data slice. This seems to help the compiler to find a RAM block which is suitable for CGC
Instead of:
wire s_wen; assign s_wen = (~CEN) ? WEN : 1'b1;
Changed to:
wire [1:0] s_wen; assign s_wen = {2 {(~CEN) ? WEN : 1'b1}};
See also attached files.
Regards
