Forum Discussion
Alexander_Kobler
New Contributor
5 years agoGated clock conversion fails due to memory
Hello Intel community,
We use "set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON" for our prototyping system, which contains several memories (RAM, ROM). Up to now, this worked as expecte...
- 5 years ago
Hi,
Thanks for pointing out these attributes, but unfortunately they do not seem to have an impact on clock gate conversion (CGC)
But I've found a solution: instead of using a single write enable (WE) for a 13 bit data word, I've used a WE for each 8 bit data slice. This seems to help the compiler to find a RAM block which is suitable for CGC
Instead of:
wire s_wen; assign s_wen = (~CEN) ? WEN : 1'b1;Changed to:
wire [1:0] s_wen; assign s_wen = {2 {(~CEN) ? WEN : 1'b1}};See also attached files.
Regards
Ash_R_Altera
Regular Contributor
5 years agoHi,
Found this Note in the Intel Quartus Prime Pro Edition User Guide: Design Compilation
Note: Automatic gated clock conversion supports explicit RAMs (such as WYSIWYG RAMs and Intel FPGA memory IP), but does not support inferred RAMs."
This explains why clock gating did not work for the new RAM component in your design.
Regards