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Altera_Forum's avatar
Altera_Forum
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17 years ago

Gate Level Synthesis: Signals

Hi, I'm facing a mismatch between my design's functional simulation and the synthesized circuit, so I thought gate level simulation would be a good start! The difficulty that I'm facing is that...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks a lot, I'll look into that then,

Cheers,