Gate Level Synthesis: Signals

I agree that the difference most of the times originates from a design issue not synthesis. In my case in fact it was a cross domain issue, but I never considered it as the boundary was Avalon, so I though it should be fine.

I've asked this in another forum too, but haven't got any answer yet, thought maybe I can ask it here too. Well, instead of using SignalTap, I though I can store my trace data in a memory module (like SDRAM) and then look at it offline. But I couldn't find a tool to easily dump a memory module's data. Is there any?! Or a function included in the nios debugger?! Thanks,

Kaveh