Gate Level Synthesis: Signals

Good thread. Some more thoughts...

SignalTap should work at almost all speeds the fabric works at. Since it directly registers the signals you're tapping, and does so in parallel, it shouldn't be a bottleneck. (Figuring out triggers and what signals to tap and how they relate back to the design can take some time though...)

I tend to worry about synthesis issues(where the synthesized circuit doesn't behave as the RTL sim) as a very last resort, and something that should be picked up by in-circuit debugging. Not that there haven't been cases where synthesis is wrong, but they're so seldom that you'd be wasting a lot of time if you didn't trust RTL sims. More often than not, I've seen users complain that something "must be getting synthesized wrong", and when we final debug the issue, it was a problem in the original RTL, just a case that hadn't been simulated or fully understood(like crossing asynchronous clock domains...)