Gate Level Synthesis: Signals

Unless you restrict synthesis, the signals found in gate level logic can't be expected to be identical to RTL. The only signals that surely survive are at the external pins. This should be sufficient to validate logic behaviour. But if you want to understand, why the behaviour is possibly different from RTL functional simulation, you may want to access internal signals. That's not so easy generally, but the equivalency of gate level and RTL is recognizable though, I think.