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Altera_Forum's avatar
Altera_Forum
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15 years ago

gate level simulations , wrong fmax

when i make gate level by linking modelsim simulator to quartus. the classic time simulator report that fmax = 170 MHz. but on gate level the output would be true only at f = 100 MHz. tha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Well.. I have seen TimeQuest fail to detect timing violations that only showed up in gate level simulations.

That said, it's very rare and I'm not 100% sure that it wasn't an user error (poorly constrained design).

So, bunch of suggestions

Even in TimeQuest, the fmax report isn't meant to be 100% reliable. Did you constrain your design to 170 MHz?

Is that the only clock in your design?

Did you constrain your inputs and outputs?