gate level simulation with time constranit

Can you put up the screenshot of your red in middle? Does your rtl simulation shows the correct value in the first place? One things to note that we don't encourage user to run the gate level timing simulation in the modelsim because it take a long time for the analysis. If possible, you run the timing analysis in the Time quest to see if there are violation. If you can, post your design.qar files here for us to have a look. Thanks