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Altera_Forum's avatar
Altera_Forum
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8 years ago

gate level simulation with time constranit

hi. I thought about this problem about days and days... I really need your help. I want to design so that maximum operating frequency is 100MHz. So I added D register in middle of my RTL code t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Can you put up the screenshot of your red in middle? Does your rtl simulation shows the correct value in the first place? One things to note that we don't encourage user to run the gate level timing simulation in the modelsim because it take a long time for the analysis. If possible, you run the timing analysis in the Time quest to see if there are violation. If you can, post your design.qar files here for us to have a look. Thanks