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Altera_Forum's avatar
Altera_Forum
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12 years ago

Gate-level simulation reported timing violations which were not reported in STA

Hi, As the title says, modelsim reported a lot of timing violations during the gate-level simulation. However the same design passed STA. I used the same clk frequency in the simulation as in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks for the reply.

Turns out the violations were due to unconstrained i/o paths. The violations disappeared when I added constraints with random parameters. Could you advice me how to determine input/output delay for specified demo board?

I'm currently implementing a NIOS system on a Terasic de4 board. Is there any document I can take reference from?