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Altera_Forum
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12 years ago

Gate-level simulation reported timing violations which were not reported in STA

Hi, As the title says, modelsim reported a lot of timing violations during the gate-level simulation. However the same design passed STA. I used the same clk frequency in the simulation as in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Timing violations can be e.g. caused by unconstrained external signals or asynchronous logic that isn't covered by timing constraints. You should analyze the nature of the timing violations.