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Hi GPK,
The timing violations is only at the beginning of the simulation. Since then, I have optimized my design and the timing violations no longer occurs.
I have another question, however. Is it possible to force fmax on the design? I have tried to Change my fitter effort under Settings > Fitter Settings > Fitter Effort from Standard Fit to Auto Fit (reduce fitter effort after meeting timing requirement). If in my SDC file, I specific a clock of 20MHz, I still sees a fmax of 200 some MHz.
Is there a way to change the settings so that Fmax of the design reflects what I have specified in SDC file?
Regards
Danny
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Hi Danny,
if you want to reduce the compile time more you can try the setting "Fast fit"., but it lookslike that your design could be very easily implement in the FPGA. The higher fmax indicates that you have a lot of margin in your design. You could choose e.g. a much slower speedgrade of the FPGA or your could do more processing during a clock cycle.
Kind regards
GPK
Honored Contributor
