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Altera_Forum's avatar
Altera_Forum
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15 years ago

Gate level simulation fail?

Hey guys, I'm trying to measure the dynamic/static power dissipated in my design which contains floating point adders and multipliers. For that I try to run the gate level simulation, write out...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi GPK,

The timing violations is only at the beginning of the simulation. Since then, I have optimized my design and the timing violations no longer occurs.

I have another question, however. Is it possible to force fmax on the design? I have tried to Change my fitter effort under Settings > Fitter Settings > Fitter Effort from Standard Fit to Auto Fit (reduce fitter effort after meeting timing requirement). If in my SDC file, I specific a clock of 20MHz, I still sees a fmax of 200 some MHz.

Is there a way to change the settings so that Fmax of the design reflects what I have specified in SDC file?

Regards

Danny