Gate level sim QTSII 10.1 / Modelsim 6.6c (both free)

For those of you interested in running a gate level sim using the Quartus tools (v10.1, modelsim 6.6c):

1 - Generate test bench:

Go to Processing->Start-> Start Test bench writer template writer

2 - Modify the test bench for driving the inputs of your design (lots of info in google)

3 - Include the test bench for automatically create the modelsim TCL script

Go to Assigments->sesttings->simulation

Then check "compile test bench", click on "test benches", a new window pops up, click on "new"

On the new window, fill in "test bench name" and "top level module in test bench" with <your_design_name>_vhd_tst

Check on "use test bench to perform VHDL timing simulation" and type i1 ( or whatever region you may be using but defaults to i1 if not changed) on "desing instance name in test bench".

Pickup the vht file you presviuosly saved clicking in "..." of the file name section. Click on "add"

Click many times ok and you will be ready for running either and RTL or a gate simulation

Hope it helps others new to Quartus 10