Gate Level Netlist

It doesn't seem that quartus_eda - the utility that dumps netlists - has a parameter to specify a top-level instance.

The closest option to what you're asking is "--vcd_tb_design_instance_name". But the output is a VCD file, not RTL.

It might also not be possible to do it at all. For example when generating flat netlists with this option: "--maintain_design_hierarchy=off". Then an instance-specific netlist looses its meaning.

Thanks,

Evgeni

Why do you want to see only modB.vhd? Does it take too long for Quartus to generate the whole gate level netlist?

What about commenting out modA and modC?

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just make modB the top level file and generate that?

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That could conceivably work as long as Quartus would synthesize it, and you don't mind the effort of creating yet another Quartus project for just one module. That was part of the motivation in the first place.

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I only want to see a specific module to check timing on that module; because it is the one that is suspect, and simulating the entire design is cumbersome and takes significant time.

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You either trust the tool or not. You don't need to check part of design for timing when you can check all design.

TQ will let you know if it passed or not assuming any multicycle paths are correct. Freezer may help or build variation etc.

In most cases it turns out to be user logic error.

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You either trust the tool or not. You don't need to check part of design for timing when you can check all design.

TQ will let you know if it passed or not assuming any multicycle paths are correct. Freezer may help or build variation etc.

In most cases it turns out to be user logic error.

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That sounds like a judgment based on design philosophy, not a specific request for the tool to do something.