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This picture is too small and low quality we cannot see the actual waveforms.
And without the test it is impossible to tell whats going on. But the appearance of U or X usually means that something is driving them that way.
You should be able to add any signal to the wave window to trace back the drivers to see what is causing the problem.
There isnt anything obviously wrong in your code., other than not assigning next_state and finito in the "others" case to cover their state when current state is "10" or "UU" or "XX". It could be something to do with this.
Otherwise I can only assume a test bench issue.
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I have to update the issue.
Decreasing the clock freq (from 100 ps to 100 ns)
The machine seems working.
The current state and current are properly updated.
So maybe i missed to look at time analysis which is the ma freq to be use with clock 
One only thing remains strange:
Signal finito and next_state[] are not synthesized
They don t appear on technology map netlist
And they cannot be monitored in Wave
Any idea about this last point?
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