gate lev sim not working as expected

following the code that works in RTL simulation but not in gate level simulation.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY somma_FSM IS
GENERIC 
	(
		WAIT_STATE :STD_LOGIC_VECTOR(1 DOWNTO 0) := B"00";
		WORK_STATE :STD_LOGIC_VECTOR(1 DOWNTO 0) := B"01";
		END_STATE :STD_LOGIC_VECTOR(1 DOWNTO 0) := B"11"
	);	
	PORT
	(
		ingressoA : IN STD_LOGIC;
		ingressoB : IN STD_LOGIC;
		inizia : IN STD_LOGIC;
		resetn :IN STD_LOGIC;
		clock : IN STD_LOGIC;
		finito : OUT STD_LOGIC;
		somma : OUT STD_LOGIC;
		resto : OUT STD_LOGIC
	);
END somma_FSM;
ARCHITECTURE somma_FSM_architecture OF somma_FSM IS
SIGNAL current_state :STD_LOGIC_VECTOR(1 DOWNTO 0) := B"00";
SIGNAL next_state :STD_LOGIC_VECTOR(1 DOWNTO 0) := B"00";
SIGNAL counter :STD_LOGIC_VECTOR(2 DOWNTO 0) := B"000";
SIGNAL resto_in :STD_LOGIC := '0';
SIGNAL resto_out :STD_LOGIC := '0';
BEGIN
PROCESS(inizia, current_state, counter)
	BEGIN
		CASE(current_state) IS
			WHEN B"00" =>
				IF (inizia = '1') THEN
					next_state <= B"01";
				ELSE
					next_state <= B"00";
				END IF;
			WHEN B"01" =>
					IF (counter = B"111") THEN
						next_state <= B"11";
--						finito <= '1';
					END IF;
			WHEN B"11"	=>
 					next_state <= B"00";
			WHEN OTHERS =>
		END CASE;
	END PROCESS;
PROCESS(clock)
BEGIN
		IF (resetn = '0') THEN
			current_state <= WAIT_STATE;
			counter <= (OTHERS => '0');
		ELSE IF ((clock'EVENT) AND (clock = '0')) THEN
			current_state <= next_state;
			IF (current_state = B"00") THEN
				counter <= (OTHERS => '0');
			ELSE IF (current_state = B"01") THEN
				counter <= counter + '1';
				resto_in <= resto_out;
				END IF;	
			END IF;
		END IF;
	END IF;	
END PROCESS;
 somma <= ingressoA XOR ingressoB XOR resto_in;
 resto_out  <= (ingressoA AND ingressoB) OR (ingressoA AND resto_in) OR (ingressoB AND resto_in);
 resto <= resto_out;
 finito <= '1' WHEN current_state =B"11";
	
END somma_FSM_architecture;