Altera_ForumHonored Contributor9 years agogate lev sim not working as expected hello everybody im quite new in developing for FPGA. I have started wih DE0-nano board. im learning just programming an easy FSM that performs elementary operations. i have followed the tut...Show More
Altera_ForumHonored Contributor9 years agowithout the code, we cant really tell what the problem is. Is the design fully syncrhonous?
Recent DiscussionsNeed a license for Encrypting - Quartus Prime LiteAgilex 5 – Critical HSSI Error in JESD204B Example Designrecovery timing issueOnce again about CTRL+Ltiming signoff