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Altera_Forum's avatar
Altera_Forum
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14 years ago

gate delays

Hi,

I need to implement a boolean function using nand and nor gates ,

and the gates should have 20ns delays. How should I change the following verilog code?

and how could I simulate the results?

is it possible to manually adjust the gate delays?

module nand ( a,b,c);

input a,b;

output c;

nand(c,a,b);

endmodule

does# 20 nand(c,a,b) work?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    First of all, that code is verilog, not VHDL.

    Secondly, you'll need to register it to get a 20ns delay (with 50Mhz clock)