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Altera_Forum's avatar
Altera_Forum
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14 years ago

gate delays

Hi, I need to implement a boolean function using nand and nor gates , and the gates should have 20ns delays. How should I change the following verilog code? and how could I simulate the result...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

First of all, that code is verilog, not VHDL.

Secondly, you'll need to register it to get a 20ns delay (with 50Mhz clock)