Forum Discussion
Altera_Forum
Honored Contributor
13 years agoWell... all the data is generated at 10MHz in a cyclon II FPGA, not sure if it will be available to do it at 256 times... but I think that I can implement paralel pipelines in a kind of trade-off between delay and registers for optimization, so... I think that it sounds kind of the idea of Kosh271 after all.