Forum Discussion
Altera_Forum
Honored Contributor
13 years agoTry something like this:
process(clkwork,reset)
begin
--first pipeline stage
if(reset = '1') then
pipeline1_0_result <= "0000";
elsif (rising_edge(clkwork)) then
if (TaoA< TaoB) then
pipeline0_0_result <= decodedBitA;
pipeline0_0_int <= TaoA;
else
pipeline0_0_result <= decodedBitB;
pipeline0_0_int <= TaoB;
end if;
if (TaoC < TaoD) then
pipeline0_1_result <= decodedBitC;
pipeline0_1_int <= TaoC;
else
pipeline0_1_result <= decodedBitD;
pipeline0_1_int <= TaoD;
end if;
--second pipeline stage
if (pipeline0_0_result < pipeline0_1_result ) then
pipeline1_0_result <= pipeline0_0_result ;
pipeline1_0_int <= pipeline0_0_int ;
else
pipeline1_0_result <= pipeline0_1_result ;
pipeline1_0_int <= pipeline0_1_int;
end if;
end if;
end process; The result is updated in pipeline1_0_result every clock with a delay. This is a 2 pipeline stage example using 4 inputs. I have written this long-hand to make it readable. It may be a good idea to wrap this into a for loop for ease of coding.