Funtion or something that finds the smaller integer

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Ok, maybe my post has a lack of information...

The decision has to be taken at each clock cicle because those Integers change at every clock cicle, there is no problem in take a little delay but would not like to take it if I don't have to.

I'm not familiar with the use of a RAM in the FPGA...

How to pipeline this? I'm not familiar with that either...

Thanks

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If your data is slow then a practical way is to run at 256 times the data rate then streamline the data and apply the algorithm:

-- clked process

if data < data_min then

data_min <= data;

end if;

at the end of stream the value will be in data_min

You need also to take care of signed/unsigned issues.

edit: from where do you get 256 data at same time? Certainly not from pins. If they are generated internal to fpga then I will assume they might be streamlined already

and you can then insert above algorithm at that point.