Forum Discussion
Altera_Forum
Honored Contributor
13 years agoOk, maybe my post has a lack of information...
The decision has to be taken at each clock cicle because those Integers change at every clock cicle, there is no problem in take a little delay but would not like to take it if I don't have to. I'm not familiar with the use of a RAM in the FPGA... How to pipeline this? I'm not familiar with that either... Thanks