Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHow fast must the decision be made to do the 'A' thing? Can you have a few cycles of delay? Is the design allowed to be pipelined? Have you considered using a RAM instead of signals?
Sorry for the large number of questions. If possible, I would end up putting the signals into a RAM and running thru the address space to determine the lowest one. (compare, remember, move on to next address) If a result is needed every clock, perhaps pipelining the design so you have a result every clock with roughly 8 clocks of delay from input to output.