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Honored Contributor
Honored ContributorFull compulation for large IO pins
Hi I would like to perform full compilation for component (not the Top Level) that has large IO pins. Im looking at over thousands bits in output bits. But I need to know the total LEs and Fmax...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- If you have large busses where bits interact with a large number of other bits, then the routing (and timing) will suffer. FPGAs benefit from pipelining, so often a design with high latency get process much more data than a huge parrallel implementation with low latency. --- Quote End --- So in that case, would inserting more pipelines would help?
