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Altera_Forum's avatar
Altera_Forum
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9 years ago

Frequency division for use in an 8x1 multiplexer

Greetings everyone, I want to design an 8x1 Multiplexing system. Starting with a frequency of (50 MHz) as the first input to the multiplexer; I want to divide this frequency by (2,3,...,8). What can ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

You can do in VHDL the same as the block diagram, and vice versa. So creating clock enables is a good idea.

Yes you can modify the VHDL after you generate it from block diagram, but you must remember to remove the block from the project and add the VHDL to the project. You cannot covert VHDL to block diagram.