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Altera_Forum's avatar
Altera_Forum
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9 years ago

Frequency division for use in an 8x1 multiplexer

Greetings everyone, I want to design an 8x1 Multiplexing system. Starting with a frequency of (50 MHz) as the first input to the multiplexer; I want to divide this frequency by (2,3,...,8). What can ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thank you indeed for your suggestion. But I'm afraid I'm using Block Diagram/Schematics for the project. Of course, I can add clk_enables to the counters, but then what?? Again I apologize for discussing non-VHDL matters here. Can I for example, manipulate with the VHDL code for the counter after I translate the blocks to VHDL?? Thanks again.