FPGA Reset

Hallo

For our project, we are using a combination Simulink HDL coder and Quartas to generate vhdl files and program the FPGA. We create our design in Simulink and using the Simulink HDL coder we generate the VHDL files. Then we use this vhdl files to create a project in Quartus and then download it in the FPGA.

We are using an Asynchronous reset. But from Quartus we get the following message

Rule R102: External reset signals should be synchronized using two cascaded registers

I have looked through the forum and understood that we need to create 2 D-flip flops to solve this problem. But Simulink HDL coder does not allow to use a D flip flop on the design. Any idea how this problem can be solved?