Forum Discussion
SKhan10
New Contributor
7 years agoFPGA Reset
Hallo For our project, we are using a combination Simulink HDL coder and Quartas to generate vhdl files and program the FPGA. We create our design in Simulink and using the Simulink HDL coder we gen...
GuaBin_N_Intel
Contributor
7 years agoAfter converting into VHDL file, you can simply add sync register chain as following https://www.intel.co.jp/content/dam/www/programmable/us/en/pdfs/literature/quartus2/qts_qii51006.pdf,figure 9-14.