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Altera_Forum
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13 years ago

FPGA device interconnects wirelength

Hello colleagues, I have a problem on the following: I need to estimate the cost of the project of connecting resources on the chip (eg, stratix III EP3SE80F1152C2). I found in a compilation rep...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

it is an indication of how much of the routing resources in the FPGA are used by the project. I'm assuming H and V means horizontal and vertical.