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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

FPGA device interconnects wirelength

Hello colleagues, I have a problem on the following: I need to estimate the cost of the project of connecting resources on the chip (eg, stratix III EP3SE80F1152C2).

I found in a compilation report in the section:

Fitter -> Resousce Section -> Logic and Routing section -> Interconnect usage summary

Which is the following:

Interconnect Resource Type Usage

Block interconnects 4,719 / 354,748 (1%)

C12 interconnects 871 / 13.114 (7%)

C4 interconnects 2,884 / 237,000 (1%)

DIFFIOCLKs 0/32 (0%)

DQS I / O Configuration Shift Register Outputs 0/104 (0%)

DQS bus muxes 0/104 (0%)

DQS-18 I / O buses 0/16 (0%)

DQS-4 I / O buses 0/104 (0%)

DQS-9 I / O buses 0/48 (0%)

Direct links 841 / 354.748 (<1%)

Global clocks 2/16 (13%)

I / O Clock Divider Clock Outputs 0/104 (0%)

I / O Configuration Shift Register Outputs 0/624 (0%)

Local interconnects 1,812 / 85,200 (2%)

NDQS bus muxes 0/104 (0%)

NDQS-18 I / O buses 0/16 (0%)

NDQS-9 I / O buses 0/48 (0%)

PLL_RX_TX_LOAD_ENABLEs 0/8 (0%)

PLL_RX_TX_SCLOCKs 0/8 (0%)

Periphery clocks 0/176 (0%)

Quadrant clocks 0/64 (0%)

R20 interconnects 640 / 14.058 (5%)

R20/C12 interconnect drivers 1,168 / 22,436 (5%)

R4 interconnects 4,321 / 400,724 (1%)

Spine clocks 10/416 (2%)

In the literature I've seen the term "overall wirelength" (typically measured in percent or nm), with which estimated the cost of connecting resources.

Tell me, is there any integral parameter? And how to calculate it?

Thank You!

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&#1071; &#1086;&#1073;&#1085;&#1072;&#1088;&#1091;&#1078;&#1080;&#1083; &#1074; &#1086;&#1090;&#1095;&#1077;&#1090;&#1077; &#1082;&#1086;&#1084;&#1087;&#1080;&#1083;&#1103;&#1094;&#1080;&#1080; &#1074; &#1089;&#1077;&#1082;&#1094;&#1080;&#1080;: Fitter -> Resousce Section -> Logic and Routing section -> Interconnect usage summary

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Interconnect Resource Type Usage

Block interconnects 4,719 / 354,748 ( 1 % )

C12 interconnects 871 / 13,114 ( 7 % )

C4 interconnects 2,884 / 237,000 ( 1 % )

DIFFIOCLKs 0 / 32 ( 0 % )

DQS I/O Configuration Shift Register Outputs 0 / 104 ( 0 % )

DQS bus muxes 0 / 104 ( 0 % )

DQS-18 I/O buses 0 / 16 ( 0 % )

DQS-4 I/O buses 0 / 104 ( 0 % )

DQS-9 I/O buses 0 / 48 ( 0 % )

Direct links 841 / 354,748 ( < 1 % )

Global clocks 2 / 16 ( 13 % )

I/O Clock Divider Clock Outputs 0 / 104 ( 0 % )

I/O Configuration Shift Register Outputs 0 / 624 ( 0 % )

Local interconnects 1,812 / 85,200 ( 2 % )

NDQS bus muxes 0 / 104 ( 0 % )

NDQS-18 I/O buses 0 / 16 ( 0 % )

NDQS-9 I/O buses 0 / 48 ( 0 % )

PLL_RX_TX_LOAD_ENABLEs 0 / 8 ( 0 % )

PLL_RX_TX_SCLOCKs 0 / 8 ( 0 % )

Periphery clocks 0 / 176 ( 0 % )

Quadrant clocks 0 / 64 ( 0 % )

R20 interconnects 640 / 14,058 ( 5 % )

R20/C12 interconnect drivers 1,168 / 22,436 ( 5 % )

R4 interconnects 4,321 / 400,724 ( 1 % )

Spine clocks 10 / 416 ( 2 % )

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7 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I don't understand your question. What is the meaning of "estimate the cost of the project of connecting resources"?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    I don't understand your question. What is the meaning of "estimate the cost of the project of connecting resources"?

    --- Quote End ---

    I need an integral charactiristic of needed connecting resourses for device in FPGA realization.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I still don't get it. What characteristics? What kind of connections? What kind of resources? What kind of devices?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    I still don't get it. What characteristics? What kind of connections? What kind of resources? What kind of devices?

    --- Quote End ---

    Logic utilization 3,345 / 64,000 ( 5 % ) !!!INTEGRAL PARAMETER!!!

    -- Difficulty Clustering Design 3602

    -- Combinational ALUT/register pairs used in final Placement 1760

    -- Combinational with no register 1227

    -- register only 615

    -- Combinational with a register 141

    -- Estimated pairs recoverable by pairing ALUTs and registers as Design grows 71

    -- Estimated Combinational ALUT/register pairs unavailable 46

    -- unavailable due to Memory LAB use 24

    -- Unavailable due to unpartnered 7 LUTs 0

    -- Unavailable due to unpartnered 6 LUTs 0

    -- Unavailable due to unpartnered 5 LUTs 0

    -- unavailable due to LAB-wide signal conflicts -398

    -- unavailable due to LAB input limits Low

    How can I get such parameter for interconnection resourses?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    In the Fitter -> Resousce Section-> Resource usage summary

    I founded such parameter:

    Average interconnect usage (total/H/V) 31% / 31% / 31%

    What it means? What is H and V?

    Thank U.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    it is an indication of how much of the routing resources in the FPGA are used by the project. I'm assuming H and V means horizontal and vertical.