Altera_Forum
Honored Contributor
12 years agoForming a tightly coupled memory system in Qsys
Hey,
I am trying to generate a custom component which is tightly coupled with the onchip memory. The problem is that the qsys exposes only the port of the onchip memory rather than the individual signals which make it up. Is there any way to interface to the individual signals of the port in qsys or any other way, where i dont have to modify by hand , after it generates the files.