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Altera_Forum's avatar
Altera_Forum
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12 years ago

Forming a tightly coupled memory system in Qsys

Hey, I am trying to generate a custom component which is tightly coupled with the onchip memory. The problem is that the qsys exposes only the port of the onchip memory rather than the individu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I am not able to find that option if there is one. I was looking at tcl_component_desicription as a way, but feels like it will take some time to get my head around it. I need to expose those signals in qsys or in some other way so that interfacing could be easier.

Would you have any suggestion on where i can find such an option.