Formal verification on modelsim (systemverilog)

Hi

I am trying to write a verification environment on the modelsim simulator.

My problem is to work the signal driver tasks (BFM) from the sequence driver (generator) when both of them are in the environment level block (agent).

////////// Drivers //////////

class Driver;

virtual SVinter SVinter_int;

function new (virtual SVinter i);

SVinter_int = i;

endfunction

task clk_drive;

input Iclk;

SVinter_int.clk = Iclk;

endtask

endclass

////////// Sequences /////////

class sequenceDrive;

task sequences;

fork

forever begin

// # 10 Driver.clk_drive(1'b1); <= this of course don't work

// # 10 Driver.clk_drive(1'b0);

end

join

endtask

endclass

//////////////////////////////

////// Main environment //////

//////////////////////////////

class environment;

virtual SVinter SVinter_int;

function new (virtual SVinter i);

SVinter_int = i;

endfunction

Driver Driver_inst;

sequenceDrive sequenceDrive;

task build_environment;

Driver_inst = new(SVinter_int);

sequenceDrive = new();

endtask

task start_test;

sequenceDrive.sequences;

endtask

Endclass

What is the best way to operate the Driver from the sequence drive?

And later I'll need to move the data struct from the monitor to the scoreboard. What is the best way to do that?

thanks