foreach in systemverilog

Yes! Of course... Quartus does not compile with foreach statement... I just assumed that it was obvious because all I use Quartus is to compile the code i.e. synthesize and p&r.

Quartus thinks it's a syntax error atleast the error seems to suggest that. Don't remember or have the exact error in front of me. But it doesn't matter any more since Altera's support indicated that "foreach" statement is not supported Quartus 12.0. Quartus 12.0 help seems to indicate all loop constructs are supported.