"Force Use of Synchronous Clear Signals" assignment

here is an example:
I create in vhdl the model of the FF I need:

DFF:process(clk_10M_int)is
begin

if rising_edge(clk_10M_int)then
if(sclr='1')then
Qdata<='0';
elsif(sload='1')then
Qdata<='1';
else
Qdata<=Ddata;
end if;
end if;

end process DFF;

then I fix the register position on a register (one of 2) outgoing DDRs with the following line in 
the .qsf file:

set_location_assignment DDIOOUTCELL_X34_Y10_N11 -to Qdata~reg0

At this point Quartus creates the circuit of the 1st photo:

then I always add this line in the .qsf file: 
set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to Qdata ~ reg0

Now Quartus creates this circuit:

So I can activate the synchronous reset of that register, 
but I don't know how to activate the synchronous load

Basically, Quartus uses combinatorial logic to create the "sync_load" function, as seen in this photo:

thank you very much for your time