Forum Discussion
LMelo2
New Contributor
New Contributor"Force Use of Synchronous Clear Signals" assignment
Good morning. I need to force the position of a particular register on DDIOOUTCELL. The "Location -> DDIOOUTCELL_X34_Y18_N4" assignment works correctly. Also I need to use the SCLR, SLOAD and SDATA p...
sload is used to set a value from a separate sdata input. You're just setting the output to 1 when this signal is enabled, which is not the intended behavior. If the device doesn't support this configuration (which seems to be the case) extra logic is added to give you the behavior you've defined.
Maybe what you really want is an asynchronous preset, which would set the output to 1 whenever enabled.
You should check the Design Recommendations user guide to see how to code for what you want:
sstrell
Super Contributor
Super ContributorHow are you coding this? It would be based on that.
LMelo2here is an example: I create in vhdl the model of the FF I need:DFF:process(clk_10M_int)is
beginif rising_edge(clk_10M_int)then
if(sclr='1')then
Qdata<='0';
elsif(sload='1')then
Qdata<='1';
else
Qdata<=Ddata;
end if;
end if;end process DFF;
then I fix the register position on a register (one of 2) outgoing DDRs with the following line in
the .qsf file:set_location_assignment DDIOOUTCELL_X34_Y10_N11 -to Qdata~reg0At this point Quartus creates the circuit of the 1st photo:then I always add this line in the .qsf file:
set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to Qdata ~ reg0Now Quartus creates this circuit:So I can activate the synchronous reset of that register,
but I don't know how to activate the synchronous loadBasically, Quartus uses combinatorial logic to create the "sync_load" function, as seen in this photo:
