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Altera_Forum
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15 years ago

For Loop Synthesis Problem

I am trying to write a function that set all bits to the right of the most significant set bit of the input word. For some reason the follow Verilog code does not work correctly in Quartus II 10.0. T...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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I know it's wrong

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As I said, I got a correct result with your above function, so I know it can be right. To make the problem observed in your usage of the function understandable, you should give a code example, that allows to reproduce it. At present, I don't expect, that the problem is related to the function itself.

For the function coding, i would prefer a form that represents the intended operation more clearly: Search the leftmost bit != 0, set all bits right of it. But the result should be identical in any case.