Occasional Contributor
Occasional ContributorIs there anything I can do?
The portion of my code in question, the middle of my 'BrianHG_DDR3_COMMANDER.sv' running on PLL CLK 4 - 100 MHz boils down to a 4:1 selector mux, ~168 bits wide, selection based on comparing 4 inputs with 4x2 compares to a stored 28 bit address easily surpasses the required 100MHz on Cyclone III, Cyclone IV, Max 10, not to mention the faster fabrics, but for some reason, it really dies on a -6 Cyclone V.
My 200MHz and 400MHz sections are nothing block shifting more than serializers, so the Cyclone V appears to be able to cope with those. But why is it such a massive downgrade from all the older FPGAs?
Even worse, if I leave the compile options on the default 'Balanced', the FMAX is only ~ 41MHz while the other Cyclones will still pass the required 100MHz. There isn't much I can do to simplify the 4:1 selection mux which feeds the next source code section of my design. Multistage pipeline would destroy the codes ability to correctly select which of the 4 inputs should be prioritized to run next.
Is there something in the Cyclone V fitter's settings which has somehow decided to massively impact the core's performance?
Or, once again, should I consider the Cyclone V to be truly a half speed FPGA and scratch it from my list of potential devices I can use?
