Fmax and Restricted Max

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Hello,

In the Time Quest, the Fmax for my design is 303 MHz , but the Restricted Fmax is 250 MHz with a Note that says 'limit due to minimum period restriction (max I/O toggle rate)' . The clock frequency = 333 MHz.

Does this mean that I need to operate the design not beyond 250 MHz or will 303 MHz work too?

Thanks

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I am afraid yes the ultimate fmax is that figure of the most restrictive case.

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The restricted fmax is usually due to the part you are using.

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Tricky.. I did not understand your reply. Can you please explain what it means?

I have a few more questions.

1) What exactly is the difference between a netlist and a timing netlist?

2) How is the Fmax and Restricted Fmax calculated? One of the report says: "Restricted fmax considers hold timing in addition to setup timing, as well as minimum pulse and minimum period restrictions. " But nothing is said about the unrestricted Fmax. Does it mean that unrestricted Fmax considers only setup time?

3) Now the restriction is only due to the width of the clock cycle and not due to the "delay" of the circuit. Will it make sense to consider Fmax and NOT restricted Fmax if we take only propagation delay into consideration?

Thank you.

1. A netlist is literally a list of nets. It could be part of a design so it may fill in a hole (black box) in the design so that it is added on during the fit stage. A timing netlist contains timing information which allows it to be simulated.

2and 3. The important thing is that you are limited to the lower of the 2 values. Do you have a specific problem? Do you have a lot of async logic?

Thank you for the reply Tricky.

No, I don't have any specific problem. I was wondering if the unrestricted Fmax can be considered so that everything is measured using just the propagation delay.

I need to report frequency values for my research where the design is not specific to Cyclone IV (which I am working on currently) or any FPGA. So using the Restricted Fmax which restricts the frequency because of pulse width limitation might not give true delay dependent value. What do you think about this?

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1) What exactly is the difference between a netlist and a timing netlist?

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Adding further to notes by Tricky,

Tools produce from your source code(or schematic entry) some other language-like text code called netlist that just describes the connections. The connections may be at logic level (i.e. your rtl as mapped to generic logic, no details of device mapping), this is rtl netlist. Or it is for connections after P&R plus delay information(which could be separate) and this is timing netlist(e.g vho). netlists may also be supported for initial design entry along with other source code. An encrypted netlist is favoured by those who want to make money. Other netlist types include edif, atom, and xilinx has ngc...etc.

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2) How is the Fmax and Restricted Fmax calculated? One of the report says: "Restricted fmax considers hold timing in addition to setup timing, as well as minimum pulse and minimum period restrictions. " But nothing is said about the unrestricted Fmax. Does it mean that unrestricted Fmax considers only setup time?

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The classic fmax was and is still calculated as follows:

minimum clock period = reg tSU + reg tCO + reg to reg data delay - reg to reg clock delay

fmax = 1/minimum clock period

note all above are fixed intrinsically per device path.

restricted fmax is relatively new concept and resulted from very fast designs in which above fmax is achieved but further restrictions arise due to

minimum pulse/period and hold violation and io toggle rate.

The restriction by hold violation is interesting and undocumented and I believe it is due to the case when clock period is so short that tCO of a launch register directly violates tH at previous latch edge at latching register even though clock/data delay is not to blame.

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3) Now the restriction is only due to the width of the clock cycle and not due to the "delay" of the circuit. Will it make sense to consider Fmax and NOT restricted Fmax if we take only propagation delay into consideration?

Thank you.

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For a given device, the worst fmax applies. But if you are thinking of a generic design that reports speed only on tSU/tCO and delay basis then you can report fmax only.

Restricted Fmax comes into play when using things like DSP and memory blocks. the timing paths inside of these blocks are not explicitly calculated using the formula that kaz lists above due to their complicated structure. instead, the datasheet specs of these blocks in their various modes are programmed into Quartus and will show up as Restricted Fmax

as others have pointed out, you'll need to look at the lower of these two numbers to see how fast your design will actually run. better yet, take a look at the Top Failing Paths or similar

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Restricted Fmax comes into play when using things like DSP and memory blocks. the timing paths inside of these blocks are not explicitly calculated using the formula that kaz lists above due to their complicated structure. instead, the datasheet specs of these blocks in their various modes are programmed into Quartus and will show up as Restricted Fmax

as others have pointed out, you'll need to look at the lower of these two numbers to see how fast your design will actually run. better yet, take a look at the Top Failing Paths or similar

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Just got this answer from Altera regarding restricted fmax due to hold check:

"Usually Fmax is not limited by hold checks as they are generally same edge relationships and therefore independent of frequency. If you have an inverted clock transfer of a multicycle transfer the hold relationship is no longer same edge but changes with frequency. If the hold check limits the Fmax more than the setup check then you will see “limit due to hold check” as the reason."

But in a project I noted fmax was 300 plus while restricetd fmax was below 200 due to hold check yet the design did not tell where is that restriction and all hold slack was positive with regard to fmax (not restricted fmax).