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1) What exactly is the difference between a netlist and a timing netlist?
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Adding further to notes by Tricky,
Tools produce from your source code(or schematic entry) some other language-like text code called netlist that just describes the connections. The connections may be at logic level (i.e. your rtl as mapped to generic logic, no details of device mapping), this is rtl netlist. Or it is for connections after P&R plus delay information(which could be separate) and this is timing netlist(e.g vho). netlists may also be supported for initial design entry along with other source code. An encrypted netlist is favoured by those who want to make money. Other netlist types include edif, atom, and xilinx has ngc...etc.
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2) How is the Fmax and Restricted Fmax calculated? One of the report says: "Restricted fmax considers hold timing in addition to setup timing, as well as minimum pulse and minimum period restrictions. " But nothing is said about the unrestricted Fmax. Does it mean that unrestricted Fmax considers only setup time?
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The classic fmax was and is still calculated as follows:
minimum clock period = reg tSU + reg tCO + reg to reg data delay - reg to reg clock delay
fmax = 1/minimum clock period
note all above are fixed intrinsically per device path.
restricted fmax is relatively new concept and resulted from very fast designs in which above fmax is achieved but further restrictions arise due to
minimum pulse/period and hold violation and io toggle rate.
The restriction by hold violation is interesting and undocumented and I believe it is due to the case when clock period is so short that tCO of a launch register directly violates tH at previous latch edge at latching register even though clock/data delay is not to blame.
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3) Now the restriction is only due to the width of the clock cycle and not due to the "delay" of the circuit. Will it make sense to consider Fmax and NOT restricted Fmax if we take only propagation delay into consideration?
Thank you.
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For a given device, the worst fmax applies. But if you are thinking of a generic design that reports speed only on tSU/tCO and delay basis then you can report fmax only.
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