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Restricted Fmax comes into play when using things like DSP and memory blocks. the timing paths inside of these blocks are not explicitly calculated using the formula that kaz lists above due to their complicated structure. instead, the datasheet specs of these blocks in their various modes are programmed into Quartus and will show up as Restricted Fmax
as others have pointed out, you'll need to look at the lower of these two numbers to see how fast your design will actually run. better yet, take a look at the Top Failing Paths or similar
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Just got this answer from Altera regarding restricted fmax due to hold check:
"Usually Fmax is not limited by hold checks as they are generally same edge relationships and therefore independent of frequency. If you have an inverted clock transfer of a multicycle transfer the hold relationship is no longer same edge but changes with frequency. If the hold check limits the Fmax more than the setup check then you will see “limit due to hold check” as the reason."
But in a project I noted fmax was 300 plus while restricetd fmax was below 200 due to hold check yet the design did not tell where is that restriction and all hold slack was positive with regard to fmax (not restricted fmax).
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