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Altera_Forum's avatar
Altera_Forum
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7 years ago

flop-flop simulation in ModelSim

i try to simulate [1:0]flip-flop in ModelSim and i see one normal signal(out_inf[0]) and one blue signal(out_inf[1]). What is it?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

dff code 


module dff(clk, din, dout); 
  input clk; 
  input  din; 
  output  dout; 
reg dout; 
 always @ (posedge clk) 
  begin 
   dout <= din; 
end 
endmodule

testbench 


module top; 
   reg clk; 
   reg  in_inf; 
   wire  out_inf;
dff D1 (clk, in_inf, out_inf); 
initial // Clock generator
  begin
    clk = 0;
    forever# 10 clk = !clk;
  end
initial //in_inf    
  begin
    in_inf = 0;
   # 28 in_inf = 1;
   # 5 in_inf = 0;
  end
initial    //in_inf    
  begin
    in_inf = 0;
   # 48 in_inf = 1;
   # 5 in_inf = 0;
  end
endmodule

i want to see normal (not blue) signal as out_inf[1]