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Altera_Forum's avatar
Altera_Forum
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12 years ago

floating number with synthetisable vhdl code

Hi,

I have to use floating number with my VHDL code wich wille be implemented in a de2 card so

how can I use floating point?? I have seen that this method use number between (-128)et 127

if I have to use number over this interval biger then 127 what can I do??

thank you.

13 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    You cannout use the IEEE floating library very well in quartus, because your maximum clock speed would be very very slow (maybe 25MHz if you're lucky). The Altera FP cores are pipelined so speeds >300MHz should be possible.

  • Altera_Forum's avatar
    Altera_Forum
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    ah ok I m working with 50 MHz frequency clock.

    there is an other way to present real number or I must use this FP core with less performance??

    thanks