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Altera_Forum's avatar
Altera_Forum
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10 years ago

float data format are simulated in Modelsim

Hi, Now, I need to simulate output data of FPGA in Modelsim which data format is signal precision . the width of single precision is 32 ,and the modelsim view those 32 bits to integer. and now...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

if you use the floating point library in the IEEE library (which is part of the VHDL 2008 spec) then coverting to real is as simple as: 


library ieee;
use ieee.std_logic_1164.all;
use ieee.float_lib.all;
....
signal a : std_logic_vector(31 downto 0);
signal r : real;
....
r <= bitstoreal(a);